Device and method of reducing junction leakage

ABSTRACT

A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.

RELATED APPLICATION INFORMATION

This application is a Divisional application of co-pending U.S. patentapplication Ser. No. 12/789,839 filed on May 28, 2010, incorporatedherein by reference in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to semiconductor devices and processingand more particularly to a structure and method for forming structuresthat reduce junction leakage.

2. Description of the Related Art

Junction leakage becomes a serious problem for low power technologiesand particularly for technologies where devices are scaled beyond a 32nm node. To control device short channel effects, dopant diffusionshould be limited. This is done by reducing the thermal budget, which inturn results in incomplete removal of the defects generated by dopantion implantation. Also, with very shallow junctions, the space between asilicide and junction becomes small, which results in excessive junctionleakage.

Raised source drain structures are considered as a way to alleviatethese problems. However, conventional raised source drain structureleads to excessive increases in the device parasitic capacitance.Depending on the integration scheme, disposable spacers might be needed,which make the process more complicated. In addition, there are concernsabout junction leakage at an edge of the shallow trench isolation (STI).Usually a divot exists at the STI edge and if the junction is not deepenough at this point, silicide formation at the STI edge causesadditional leakage.

SUMMARY

A device and method for reducing junction leakage in a semiconductorjunction includes forming a faceted raised structure in a source/drainregion of the device. Dopants are diffused from the faceted raisedstructure into a substrate below the faceted raised structure to formsource/drain regions. A sprinkle implantation is applied on the facetedraised structure to produce a multi-depth dopant profile in thesubstrate for the source/drain regions.

Another method for reducing junction leakage in a semiconductor deviceincludes forming device isolation structures in a substrate; forming agate stack having a first spacer formed on lateral sides thereof on thesubstrate; forming a faceted raised structure in a source/drain regionof a device; diffusing dopants from the faceted raised structure intothe substrate below the faceted raised structure to form source/drainregions; applying a sprinkle implantation on the faceted raisedstructure to produce a multi-depth dopant profile in the substrate forthe source/drain regions; and forming a silicide on the faceted raisedstructures.

A semiconductor device includes a gate stack formed on a semiconductorsubstrate and source/drain regions formed adjacent to the gate stackhaving faceted raised structures formed on the substrate and havingdiffused dopant regions in the substrate below the faceted raisedstructures. A multi-depth dopant profile is formed in the substrate forthe source/drain regions to reduce junction leakage.

A semiconductor device includes a gate stack formed on a semiconductorsubstrate and source/drain regions formed adjacent to the gate stackhaving faceted raised structures formed on the substrate and havingdiffused dopant regions in the substrate below the faceted raisedstructures. A multi-depth dopant profile is formed in the substrate forthe source/drain regions. The multi-depth dopant profile extends betweenthe gate stack and a shallow trench isolation region and has a greatestdepth at the shallow trench isolation region to reduce junction leakage.The greatest depth corresponds to the facets of the faceted raisedstructure.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a prior art MOSFET;

FIG. 2 is a cross-sectional view of a substrate having shallow trenchisolation regions and a gate stack formed thereon in accordance with oneillustrative embodiment;

FIG. 3 is a cross-sectional view of the substrate of FIG. 2 havingfaceted raised portions formed on the substrate and diffused dopantregions formed below the faceted raised portions in accordance with oneillustrative embodiment;

FIG. 4 is a cross-sectional view of the substrate of FIG. 3 having asecond spacer formed and a sprinkle implant, which forms a multi-depthdopant profile below the faceted raised portions in accordance with oneillustrative embodiment;

FIG. 5 is a cross-sectional view of a semiconductor device havingreduced junction leakage in accordance with one illustrative embodiment;and

FIG. 6 is a flow diagram showing a method for reducing junction leakagein a semiconductor device in accordance with one embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A faceted epitaxially raised source/drain structure and method aredescribed to reduce the junction leakage in accordance with oneembodiment. Source/drain (S/D) implantation is avoided to eliminate thegeneration of defects. A shallow junction is obtained whichsignificantly reduces the junction capacitance and improves device shortchannel control. A low-dose “sprinkle” implant is used, which employsthe facet nature of the epitaxial layer to reduce junction leakage at anedge of a shallow trench isolation (STI).

It is to be understood that the present invention will be described interms of a given illustrative architecture; however, otherarchitectures, structures, substrate materials and process features andsteps may be varied within the scope of the present invention. Thecircuit as described herein may be part of a design for an integratedcircuit chip. The chip design may be created in a graphical computerprogramming language, and stored in a computer storage medium (such as adisk, tape, physical hard drive, or virtual hard drive such as in astorage access network). If the designer does not fabricate chips or thephotolithographic masks used to fabricate chips, the designer maytransmit the resulting design by physical means (e.g., by providing acopy of the storage medium storing the design) or electronically (e.g.,through the Internet) to such entities, directly or indirectly. Thestored design is then converted into the appropriate format (e.g.,GDSII) for the fabrication of photolithographic masks, which typicallyinclude multiple copies of the chip design in question that are to beformed on a wafer. The photolithographic masks are utilized to defineareas of the wafer (and/or the layers thereon) to be etched or otherwiseprocessed.

The methods as described herein may be used in the fabrication ofintegrated circuit chips. The resulting integrated circuit chips can bedistributed by the fabricator in raw wafer form (that is, as a singlewafer that has multiple unpackaged chips), as a bare die, or in apackaged form. In the latter case the chip is mounted in a single chippackage (such as a plastic carrier, with leads that are affixed to amotherboard or other higher level carrier) or in a multichip package(such as a ceramic carrier that has either or both surfaceinterconnections or buried interconnections). In any case the chip isthen integrated with other chips, discrete circuit elements, and/orother signal processing devices as part of either (a) an intermediateproduct, such as a motherboard, or (b) an end product. The end productcan be any product that includes integrated circuit chips, ranging fromtoys and other low-end applications to advanced computer products havinga display, a keyboard or other input device, and a central processor.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a prior art devicestructure 10 is shown for comparative purposes. Device 10 shows aconventional metal oxide semiconductor field effect transistor (MOSFET)structure. Source/drain (S/D) extensions 17 and deep S/D junctions 18are formed by implanting dopant atoms into the substrate 12,respectively, after first spacers 26 and second spacers 28 are formed tooffset the junction 18 from a channel 20. To obtain shallow junctions,thermal budget to anneal the implants should be reduced, but this leadsto an incomplete removal of the defects 22 caused by the high-dose ionimplant. In addition, the so-called transient enhanced diffusion whichis caused by excess point defects generated by ion implantation makes itdifficult to obtain shallow junctions.

The structure 10 includes the semiconductor substrate 12 having devicesseparated by shallow trench isolation regions 14. Source and drainjunctions 18 have a silicide 20 formed thereon. Junction leakage occursespecially at an edge of the shallow trench isolation (STI) 14. Usuallya divot 24 exists at the STI edge and if the junction 18 is not deepenough at this point, silicide formation at the STI edge causesadditional leakage.

Implantation of source/drain regions generates implant defects 22 in thejunction area 18. Junction leakage occurs especially at an edge of theshallow trench isolation (STI) 14. Usually a divot 24 exists at the STIedge and if the junction 18 is not deep enough at this point, silicideformation at the STI edge causes additional leakage.

Device 10 includes a gate stack 25 having a gate conductor 27 and a gatedielectric 29. First spacers 26 and second spacers 28 are formed onlateral sides of the gate stack 25.

Referring to FIG. 2, a partially fabricated semiconductor device 100 isillustratively shown in accordance with one embodiment. Device 100includes a semiconductor substrate 112 having device regions separatedby shallow trench isolation (STI) regions 114. The substrate 112 mayinclude a suitable substrate material, for example, substrate 112 mayinclude Gallium Arsenide, monocrystalline silicon, Germanium, bulkmaterials or any other material or combination of materials. In someembodiments, the substrate 112 further comprises other features orstructures that are formed on or in the semiconductor substrate inprevious process steps. The STI regions 114 may include an oxide, suchas a silicon dioxide or other dielectric material. A divot 116 forms atthe upper most interface between the substrate 112 and the STI material(114). This divot 116 forms as a result of normal processing and is noteasily avoided.

Device 100 includes a gate stack 124 having a gate conductor 125 and agate dielectric 127. Spacers 126 have been formed on the gate stack 124and may include a silicon nitride or other suitable material. Areas 129adjacent to the gate stack 124 are employed in forming a source and adrain for the device 100.

Referring to FIG. 3, after device isolation using STI 114, formation ofthe gate stack 124, and the formation of the first spacer 126 as shownin FIG. 2, a faceted epitaxial layer 130 is formed in source/drainregions. This layer 130 can be grown with in-situ dopants present at thetime of formation of the epitaxial grown layer 130, or the layer 130 canbe implanted with dopant species after its initial deposition. Layer 130may include a crystalline silicon material, silicon germanium, siliconcarbide, in-situ boron doped silicon germanium, in-situ phosphorousdoped silicon carbide, in-situ phosphorous doped silicon, in-situarsenic doped silicon, in-situ phosphorous doped silicon germanium, etc.Layer 130 is implanted with dopants, which include B, BF₂ or otherp-type dopants for p-type devices and include As, P or other n-typedopants for n-type devices.

In one embodiment, an annealing step is performed to drive in thedopants from the layer 130 to the substrate 112 and form S/D extensions134. Optionally, an implant can be done from the area between a facet133 of layer 130 and the gate spacer 126 to form the extension 134 or tocontrol the diffusion of the dopants prior to the annealing step. Thisstep may be implemented by forming a masking layer (not shown) toprotect other areas of the device from the implantation. Optional haloimplants may also be performed after the extension 134 formation throughthe space between the facet 133 and the spacer 126. Depending on themethod for forming the extensions 134, dopant densities of between about1×10¹⁹/cm³ and 8×10²¹/cm³ are preferable. The halo implants are mayinclude dopants such as B, BF₂, In, As, etc. having a density of betweenabout 1×10¹⁸/cm³ and 5×10²⁰/cm³.

Referring to FIG. 4, a second spacer 128 is formed over the first spacer126 and includes a similar material (e.g., silicon nitride). A low-doseimplant (e.g., dose between about 1×10¹³ cm⁻² to about 1×10¹⁴ cm⁻²) isperformed. An illustrative energy level includes, e.g., 2-50 KeVdepending on thickness (e.g., Si thickness). The low-dose implant may bereferred to as a “sprinkle” implant to distinguish it from normalimplantation.

In the area near the STI 114 where the epitaxially formed layer 130 hasfacets 133, the sprinkle implant penetrates deeper into the substrate112 at portion 140, while in the rest of the S/D region, the implant isnot as deep in portion 142. So, while the S/D junction/extension 134 isshallow for the most part as defined by the dopant drive-in, near theSTI edge, the junction is deeper in portion 144. The deeper portions 140and 144 (and shallow portions 142) result from the faceted geometry ofthe layer 130. Optionally, the low-dose implant can be performed at anangle A to provide an even deeper junction at the location of the divot116.

A relatively low thermal budget anneal is done to activate the dopantsfrom the low-dose implant (sprinkle implant). This can be a lowtemperature spike anneal, e.g., less than or equal to about 1000° C., alaser anneal, a msec anneal or a combination of these. Silicide 150(FIG. 5) is then formed and complementary metal oxide semiconductor(CMOS) processing continues as normal.

Referring to FIG. 5, a completed structure 200 for an exemplary deviceis illustratively shown. A faceted epitaxially raised source/drainstructure 202 is provided which along with other features reducesjunction leakage. Advantageously, S/D implantation, which generatesdefects at the junction interface is avoided to eliminate the generationof these defects. Instead, a shallow junction 118 is obtained whichsignificantly reduces the junction capacitance and improves device shortchannel control. A low-dose “sprinkle” implant is provided to form amulti-depth dopant profile 148 in the substrate, which employs the facetnature of the raised structure 202 to reduce junction leakage at the STIedge.

Silicide 150 is formed over the structures 202 and can even cover alateral portion of the junction 118 in the divot 116. With reducedcapacitance and junction leakage, significant performance benefits areachieved, and long term effects of implant defects are avoided, amongother things.

Referring to FIG. 6, a method for fabrication of a device with improvedjunction leakage performance is illustratively depicted. In block 302,device isolation regions or shallow trench isolation regions are formedin a substrate. In block 304, a gate stack is formed, which may includea gate oxide, gate conductor, and a first spacer. In block 306, afaceted raised structure is formed in a source/drain region of asemiconductor device. The faceted raised structure may includeepitaxially growing the faceted raised structure on a surface of thesubstrate.

In block 308, dopants may be provided in-situ during the formation ofthe faceted raised structure, or dopants may be implanted into thefaceted raised structure after formation of the faceted raised structurein block 310. In block 312, these dopants are diffused from the facetedraised structure into the substrate below the faceted raised structureto form source/drain regions. This may be assisted by annealing thedevice.

In block 314, a second spacer may be formed after forming the facetedraised structure. In block 316, a sprinkle implantation may be appliedon the faceted raised structure to produce a multi-depth dopant profilein the substrate for the source/drain regions. The sprinkle implantationmay provide a dose of between about 1×10¹³ cm⁻² to about 1×10¹⁴ cm². Themulti-depth dopant profile may include a greater depth corresponding tofacets of the faceted raised structure. The multi-depth dopant profilepreferably extends between a gate stack and a shallow trench isolationregion and the multi-depth dopant profile includes a greatest depth atthe shallow trench isolation region. The multi-depth dopant profile ispreferably formed by a combination of a shape of the faceted raisedstructures and dopant implant conditions to provide dopants at differentdepths. In block 318, a silicide is formed on the faceted raisedstructures. In block 320, processing continues to complete the device.

Having described preferred embodiments of a device and method forreducing junction leakage (which are intended to be illustrative and notlimiting), it is noted that modifications and variations can be made bypersons skilled in the art in light of the above teachings. It istherefore to be understood that changes may be made in the particularembodiments disclosed which are within the scope of the invention asoutlined by the appended claims. Having thus described aspects of theinvention, with the details and particularity required by the patentlaws, what is claimed and desired protected by Letters Patent is setforth in the appended claims.

What is claimed is:
 1. A semiconductor device, comprising: a gate stackformed on a semiconductor substrate; source/drain regions formedadjacent to the gate stack having faceted raised structures formed onthe substrate and having diffused dopant regions in the substrate belowthe faceted raised structures; and a multi-depth dopant profile formedin the substrate for the source/drain regions to reduce junctionleakage, the multi-depth dopant profile for at least one of thesource/drain regions having a shallow portion between a first deepportion and a second deep portion.
 2. The device as recited in claim 1,wherein the multi-depth dopant profile extends between the gate stackand a shallow trench isolation region and having a greatest depth at theshallow trench isolation region.
 3. The device as recited in claim 1,wherein the faceted raised structure includes a facet adjacent to thegate stack and a facet adjacent to the shallow trench isolation region.4. The device as recited in claim 1, wherein the gate stack includes afirst spacer formed before the faceted raised structure, and a secondspacer formed after the faceted raised structure.
 5. The device asrecited in claim 4, wherein the second spacer is formed over the firstspacer and a portion of the faceted raised structure.
 6. The device asrecited in claim 1, wherein the multi-depth dopant profile includes agreater depth corresponding to facets of the faceted raised structure.7. The device as recited in claim 1, further comprising a silicideformed on the faceted raised structure.
 8. The device as recited inclaim 1, wherein the multi-depth dopant profile is formed by acombination of a shape of the faceted raised structures and dopantimplant conditions to provide dopants at different depths.
 9. Asemiconductor device, comprising: a gate stack formed on a semiconductorsubstrate; source/drain regions formed adjacent to the gate stack havingfaceted raised structures formed on the substrate and having diffuseddopant regions in the substrate below the faceted raised structures; anda multi-depth dopant profile formed in the substrate for thesource/drain regions, the multi-depth dopant profile extending betweenthe gate stack and a shallow trench isolation region and having agreatest depth at the shallow trench isolation region to reduce junctionleakage, the greatest depth corresponding to the facets of the facetedraised structure.
 10. A semiconductor device, comprising: a gate stackformed on a semiconductor substrate; source/drain regions formedadjacent to the gate stack having faceted raised structures formed onthe substrate and having diffused dopant regions in the substrate belowthe faceted raised structures; and a multi-depth dopant profile formedin the substrate for the source/drain regions to reduce junctionleakage, the multi-depth dopant profile having a greatest depth at ashallow trench isolation region.